SiFive announced the Arduino Cinque, the new RISC-V based development board

By on June 15, 2017
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The Arduino Cinque is the second RISC-V based development board put out by SiFive, the first being the HiFive1, which held a successful crowdfunding campaign late 2016 and is compatible with the Arduino platform.

“By partnering with a pioneer in open-source hardware, SiFive can further advance the progress of open custom silicon among makers, system designers and everyone else in between,” stated Jack Kang, VP of product and business development at SiFive. “We look forward to seeing the community’s reaction to the Arduino Cinque board, and believe that the Arduino concepts of openness and distribution mean that more people than ever will be exposed to RISC-V.”

So far only prototypes of the Arduino Cinque were available, but what is known is that the board will be hosted on SiFive’s Freedom E310 customizable SoC, which runs off the E31 CPU Coreplex (32-bit RV32IMAC Core): the Freedom E310 claims to be the fastest microcontroller on the market, capable of running at 320 MHz.

The Arduino Cinque will also have built-in Wi-Fi and Bluetooth capabilities with the inclusion of an efficient, low-power Espressif ESP32 Wi-Fi/Bluetooth hybrid chip.

The RISC-V Foundation has been actively working to spread the idea and benefits of the open-source ISA, regularly hosting workshops, participating in conferences, and collaborating with academia and industry.The announcement of the Arduino Cinque occurred the day before a panel discussion titled “Manufacturing Your Own Chips: Is Open Source (like RISC-V) Making it Easier?” at the Maker Faire Bay Area, which featured the man who coined the term “RISC”, David Patterson.

Freedom E310 Specifications

  • E310 CPU Coreplex (32-bit RV32IMAC core)
  • 320 MHz operating speed
  • 16KB L1 Instruction Cache
  • 16KB Data SRAM Scratchpad
  • Hardware multiply/divide
  • Debugging module
  • One-time programmable non-volatile memory (OTP)
  • On-chip oscillators and PLLS
  • UART, QSPI, PWM, and timer peripherals
  • Low-power standby mode

RV32IMAC Specifications

  • RV32I  Base Integer Instruction Set, Version 2.0
  • “M” Standard Extension for Integer Multiplication and Division, Version 2.0
  • “A” Standard Extension for Atomic Instructions, Version 2.0
  • “C” Standard Extension for Compressed Instructions, Version 1.9
  • RISC-V Privileged ISA Specification, Version 1.9.1
  • RISC-V External Debug Support, Version 0.11

Espressif ESP32 Specifications

  • 240 MHz dual core Tensilica LX6 micrcontroller
  • 520KB SRAM
  • 802.11 BGN HT40 Wi-Fi transceiver, baseband, stack, and LWIP
  • Classic and BLE integrated dual mode Bluetooth
  • 16 MB flash memory
  • On-board PCB antenna
  • IPEX connector for use with external antenna
  • Ultra-low noise analog amplifier
  • Hall sensor
  • 32 KHz crystal oscillator
  • GPIOs for UART, SPI, I2S, I2C, DAC, and PWM

About Luca Ruggeri

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  1. Pingback: Linux-Ready RISC-V 64-Bit Multicore CPU: SiFive U54-MC Coreplex IP | Open Electronics

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