Shakti RISC-V based Processor: the First Open Source Indian Chip

By on August 7, 2018
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Shakti is an open-source initiative by IIT Madras aimed at developing industrial-grade processors based on RISC-V.

This open source RISC-V processor is developed by students in India with assistance from Intel and its 22nm FinFET Technology. These chips are based on the RISC-V ISA from UC Berkley.

The SHAKTI processor project aims to build 6 variants of processors based on the RISC-V ISA:

C class microcontrollers

  • 32-bit 3-8 stage in-order variant aimed at 50-250 Mhz microcontroller variants
  • Optional memory protection Very low power static design
  • Fault Tolerant variants for ISO26262 applications
  • IoT variants will have compressed/reduced ISA support

I class processors

  • 64-bit, 1-4 core, 5-8 stage out of order, aimed at 200-1Ghz industrial control / general purpose applications
  • Devices aimed at networking applications will have dual-quad issue support
  • Other features – shared L2 cache, AXI bus, threading support

M Class processors

  • Enhanced variants of the I-class processors aimed at general purpose compute, low end server and mobile applications
  • Enhancements over I class – large issue size, quad-threaded, up to 8 cores, freq up to 2.5 Ghz, optional NoC fabric

S class processors

  • 64-bit superscalar, multi-threaded variant for desktop/server applications.
  • 1.2-3Ghz, 2-16 cores, crossbar/ring interconnect, segmented L3 cache
  • RapidIO based external cache coherent interconnect for multi-socket applications (up to 256 sockets)
  • Hybrid Memory Cube support
  • 256/512 bit SIMD
  • Specialized variants with FUs for database acceleration, security acceleration.
  • Experimental variants will be used as test-bed for our Adaptive System Fabric project which aims to design a data-center architecture using NV RAM devices and unified interconnects for memory, storage and networking and leverages persistent memory techniques

H class processors

  • 64-bit in-order, multi-threaded, HPC variant with 32-100 cores
  • 512 bit SIMD
  • Interconnect TBD
  • Goal is 3-5 + Tflops (DP, sustained)

T class processors

  • Experimental security oriented 64-bit variants with tagged ISA, single address space support, decoupling of protection from memory management.

While the cores and most of the SoC components (including bus and interconnect fabrics) will be in open source, some standard components like PCIe controller, DDR controller and PHY IP will be proprietary 3rd part IP.

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