SiFive Coreplex IP designs have become the leader for RISC-V cores

By on May 7, 2017
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The RISC-V open-source architecture, created by researchers at the University of California, Berkeley, in 2010, is open to all who want to use it. The RISC-V design can be modified for PCs, servers, smartphones, wearables, and other devices.

RISC-V shares the ethos of open-source software, with the community working together to share, advance, and modify the architecture.

Since the project’s inception, the interest in RISC-V has ballooned, with some of the big IT companies (like Google, Nvidia, AMD, Microsoft…)  showing interest in the architecture.

A startup called SiFive is the first to make a business out of the RISC-V architecture. The company is also the first to convert the RISC-V instruction set architecture into actual silicon. SiFive’s Coreplex IP has demonstrated significantly better power efficiency compared to other, competing ISAs (open RISC-V instruction set architecture).

SiFive few days ago revealed two initial Coreplex design configurations:

  • E31 Coreplex – The most deployed RISC-V core in the world, the E31 Coreplex is designed for low power, high performance, 32-bit embedded applications such as Edge Computing, Smart IoT or Wearables.
  • E51 Coreplex: A 64-bit embedded core, the E51 Coreplex is the ideal solution to act as a system or host control core inside larger 64-bit SoCs, as its small size and performance efficiency set it apart from the typical, bloated and large 64-bit processors while still maintaining full software compatibility with mainstream toolchains.

The RISC-V Foundation has aggressively promoted the architecture, because it has a different design than the highly integrated x86, Power, and to an extent, the ARM designs. It’s modular, meaning that independent co-processing circuits can be attached to the central RISC-V design. For example, a security or networking coprocessor can be tacked onto the core design. That makes the RISC-V highly flexible.



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