- NIXIE STYLE LED DISPLAYPosted 2 months ago
- TOTEM: learning by experimentingPosted 3 months ago
- Google Assistant Voice Controlled Switch – NodeMCU IOT ProjePosted 3 months ago
- Water Softener Salt Level MonitorPosted 3 months ago
- Sparkly Air SensorPosted 3 months ago
- Ultra sonic distance finder with live statusPosted 3 months ago
- Windows interface to have total control over lampsPosted 3 months ago
- Smart AquariumPosted 3 months ago
- Wearable ProjectionPosted 3 months ago
- Write programs with the Arduino Web EditorPosted 4 months ago
Antmicro and Thales will work together around the RISC-V open ISA
Antmicro, a software-driven high tech company developing leading industrial cyber-physical and edge AI systems, and a Platinum Founding Member of the RISC-V Foundation, has publically announced its partnership with Thales around the disruptive RISC-V open processor architecture. The companies have joined efforts to drive RISC-V into global academia and the industry at large by introducing the RISC-V paradigm into the aerospace prime’s technology tree.
“The fact that Thales is working with us to release the TMR RISC-V demonstrator and the related training materials on an open source license is an encouragement for the global industry to embrace the multifaceted technological advance that comes with the world switching to open standards on a level as fundamental as silicon…
…RISC-V adoption continues to be driven by the needs of end applications and the Antmicro / Thales collaboration is a great example of industry, technology and academia coming together to facilitate the much awaited change in computer architecture and design”, Rick O’Connor, Executive Director of the non-profit RISC-V Foundation, explains.
The company’s partnership with Thales is another step in Antmicro’s strategy and commitment to becoming a leading technology provider of RISC-V solutions.
The Triple-Modular-Redundancy RISC-V demonstrator has been designed to show how the open RISC-V ISA architecture specification, and an open source implementation thereof, can be used to build a flexible and extendible fault-tolerant voter CPU system mitigating Single Event Upset (SEU) with minimum impact on software.
A wide array of technologies is employed in the demonstrator project to achieve Triple-Modular-Redundancy in relatively short time, and to serve as a future-proof development and training platform. RISC-V lies at the base of the solution, enabling the customized CPU demonstrator to be managed with off-the-shelf, open source tools developed by the entire RISC-V ecosystem.
Click here for the full press release.